The present invention relates to structural tests for digital circuits in general, and more particularly to developing test patterns to detect timing-related failures in large digital integrated circuits.
Digital integrated circuits (ICs) are commonly fabricated with complimentary metal-oxide semiconductor (CMOS) transistors. Modern fabrication techniques have allowed smaller and faster CMOS devices to be fabricated on an IC die. One result is that very sophisticated architecture can now be implemented, including for example microprocessors. But as digital ICs become increasingly more complex, it becomes more challenging using prior art testing methodologies to thoroughly and effectively test and evaluate ICs to ensure proper device function.
Structural tests are carried out on ICs to identify those which contain a manufacturing imperfection and are to be rejected. A test signal or pattern of test signals is coupled to an input pin of a device, a digital gate for example, and the resultant signal at the output device pin is examined. Each input and output of a gate is referred to herein as a pin, and can be used to connect via a wire to one or more other gate pins. A logical gate performs a Boolean operation, e.g., AND, OR, etc. by evaluating input signal voltage levels and by yielding an output that can be coupled as input to other gates. Gates are designed according to rules for a given process technology, and may be stored in a library for use by logic designers wishing to implement functional blocks.
Structural tests for use with digital ICs may be categorized as static or dynamic. A static failure is evidenced by an incorrect response from the device regardless of how slowly or rapidly the device is operated. When sampling voltage levels, static failures may be detected after application of a single test pattern of signals to the device. A dynamic failure is evidenced by an incorrect response when the device is operated at or near its operational speed. When sampling voltage levels, detecting dynamic failures requires application of a two-pattern sequence for their detection. In practice, several test techniques may be used to detect defective digital devices, using voltage or current measurements.
A series of tests intended to detect defective devices can be developed from a simulation model of the device that is typically developed at the gate level. A gate level netlist is one way of modeling the device at the gate level. A gate level netlist is a text file specifying the gates that are connected together by wires (or nets) to implement a given function.
Using prior art testing methodology, it is not possible to characterize all possible types of incorrect operation behavior resulting from manufacturing defects for a large or complex design. As a result, fault models have been created to try to cope with the problem, where a fault model is typically a gate level modeled simplified view of incorrect behavior. A fault model defines criteria for fault detection, and an effective fault model will provide coverage to detect many kinds of defects when used to produce tests.
Testing digital circuits for incorrect behavior involves using a pattern generator to provide a pattern of input values (or vectors) to target one or more fault sites, where xe2x80x9cfault sitexe2x80x9d refers to a pin on a gate for which a test is developed to determine functionality. The term xe2x80x9cfault sitexe2x80x9d does not necessarily mean there is something wrong with a given pin since every input and output pin is included in a complete fault list.
During early test stages, any pattern, whether random or specific to a certain fault site, may fortuitously detect many non-target fault sites. Fortuitous coverage of fault sites occurs when a vector satisfies criteria for fault detection on pins other than a target fault site. If the pattern covers a fault site then the fault site is said to be xe2x80x9cdetectedxe2x80x9d and the fault site is removed or xe2x80x9cdroppedxe2x80x9d from the list of faults to be attempted or tested with the pattern generation process. Due to the nature of circuits, some fault sites are attempted but will not be detected. In practice, patterns are generated until all the fault sites on the list are either detected or attempted.
Several types of fault models are known in the relevant art. The xe2x80x9cstuck-at faultxe2x80x9d model is a widely used fault model for structural testing that detects a static fault. The stuck-at fault model assumes that a gate pin is stuck at a logic xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d voltage level. Detection of a stuck-at fault involves applying a single pattern that asserts a logic level opposite to the assumed stuck-at value, as well as other values to allow the propagation of the fault-effect to an observable destination. The term xe2x80x9cdetection of a stuck-at faultxe2x80x9d does not mean that a problem exists with the fault site. Rather the term means that if a problem exists, the pattern applied to the netlist will detect the problem. The other values that allow propagation of the fault-effect are called xe2x80x9cnon-controllingxe2x80x9d input states or values. When the pattern generator identifies a pattern or patterns that results in detection of a potential defect at a pin, that pin is then sensitized for the fault model. Unfortunately, one shortcoming with stuck-at fault testing is that timing related problems go undetected since the stuck-at test reveals only static failures.
Another fault model is the xe2x80x9ctransition faultxe2x80x9d model, which can be thought of as a stuck-at fault model extended over a two-pattern sequence, or a test for dynamic failures. Two types of transition faults are considered to exist on input pins and output pins of logic gates. A slow-to-rise type transition behaves as a stuck-at-zero fault for some temporary period of time, and a slow-to-fall type transition behaves as a stuck-at one fault for some temporary period of time. Two distinct patterns applied successively are required to switch the transition fault site. The first pattern sets the fault site at a 1 or 0 logic level, and the second pattern sets the fault site to the complementary level. Additional values are present to allow successful propagation of an injected stuck-at fault at the fault site to an observable node. A test that targets a transition fault will detect a dynamic failure when the two-pattern sequence is applied with a delay between application of the first and second patterns approximating operational speed of the device. For the transition fault to be detected, the input or output pin of the fault site must change states (0-to-1 or 1-to-0) between the two-pattern sequence. Additionally, if the fault site is at an input pin, then all other input pins on that gate must have non-controlling states or values during the second of the two-pattern sequence. The transition fault on the input pin is considered detected if these two requirements are met and if the injected fault successfully propagates to an observable destination. Advantageously, transition fault modeling provides coverage information as to number of detected faults as a percentage of the total.
Although transition fault modeling can develop tests for timing related failures, the nature of the test is quantitative rather than qualitative. The ability of a transition fault model to sensitize a delay defect associated with the transition fault site is related to paths that can be tested through the transition fault site. Value propagation through a transition fault site can be sensitized on paths having a very short delay, also called xe2x80x9cgreatest slackxe2x80x9d, or on paths having a very long delay quite near the allotted time interval, or xe2x80x9cleast slackxe2x80x9d. If the transition fault is sensitized on a path with a short delay, such additional delay contributed by a defect may not be great enough to exceed the allotted time interval. In such case, the defect will escape detection even though it is identified for testing. The transition fault model not only marks transition faults detected when sensitized on short paths, it (by nature in its implementation in commercial tools) favors their sensitization on short paths. Consequently, transition fault modeling is less likely to identify the paths most in need of dynamic testing, which are the least slack paths.
A third fault model is the xe2x80x9cpath delay faultxe2x80x9d model, a model that attempts detection of a least slack path. Unfortunately, in practice an unsensitized path is often produced during path generation. This results in prohibitive runtimes by the pattern generator for the paths supplied to it, since so many paths are unsensitizable and sensitizing path delay faults is more complex than sensitizing single stuck-at faults. Also, a path delay fault model does not provide a next least slack path to test in case a first path is untestable. Further, the pattern generation flow based on the path delay fault model is ill-equipped to provide a next least slack path in case the least slack path is untestable. The produced result is qualitative but not quantitative.
In summary, there is a need for improvement in structurally testing devices. In particular, there is a need for improvement of developing test patterns for detecting timing related failures in large digital ICs. Preferably such improved testing should provide qualitative and quantitative information for faults tested, should avoid exponential runtimes for path generation, and should identify least slack paths. Preferably the development of such test patterns should be carried out using existing software and hardware, and should reveal even small delay defects that might go undetected using prior art testing techniques. Preferably such testing should reliably extract the longest delay path through every pin on every gate in a device using two static traverses of a levelized gate netlist.
The present invention provides such a testing method.
The present invention provides test patterns to detect timing related failures in large digital ICs, to rapidly detect least slack paths. Such digital ICs typically include a plurality of gates, such that each gate has at least one input pin and at least one output pin. An output pin of a first gate is coupled to the input pin of a second gate through a wire. The present invention reduces the number of tests on the IC by determining the slowest path through the pins on the gates. This path is used to test the slowest path through each pin on every gate in the circuit. A delay value through each gate in the circuit is calculated, as well as a value for branch depth and a value for branch width. The invention determines a least slack path based on the delay, branch depth, and branch width. Further calculations are performed for reconvergent fanout and detection of fortuitous faults along one or more fanout-free regions.
The invention identifies a path (the least slack path) upon which a timing related error at a fault site is more likely to be triggered by a pattern intended to detect the fault site. The present invention also extends the functionality of a transition fault model by determining a delay value associated with a detected transition fault and thereby provides a qualitative measure of delay test coverage. A list of fault sites tested is produced, providing information as to the total degree of coverage. The development of such test patterns according to the present invention provides qualitative and quantitative information for faults tested, and avoids exponential runtimes for path generation. The present invention develops such test patterns using existing software and hardware, and can reveal small delay defects that might go undetected using prior art testing techniques. Such testing reliably extracts the longest delay path through every pin on every gate in a device using two static traverses of a levelized gate netlist.
Other features and advantages of the invention will appear from the following description in which the preferred embodiments have been set forth in detail, in conjunction with the accompanying drawings.